In the formation of semiconductor devices, it is beneficial to provide both desired electrical contact between certain regions of the devices formed and also to prevent contact between various other regions of the devices formed on the substrate. One technique for accomplishing this has been by using photoresist and masking techniques wherein those areas to be exposed for electrical contact are patterned in the photoresist, and then by developing the patterned photoresist, to thereby expose the desired underlying regions. This technique normally utilizes several successive masks to perform the entire process, and in its performance each succeeding mask must be precisely aligned. However, as the technology advances, allowing for formation of smaller and smaller devices, it is increasingly difficult to maintain precise overlay tolerance, with the result that even small misalignments of the masks will result in the exposure of small portions or “borders” of regions that are intended to remain covered. Hence, electrical connections, e.g. by an overlay deposition of a metal, may connect not only the desired locations, but also those exposed border portions of the undesired locations.
In view of this, what has been referred to as borderless contacts have been fabricated. However, in the case of for instance SRAM cells, a limiting factor for shrinking the cells is the contact to diffusion with respect to gate-conductor. This limiting factor ensures that the diffusion contact does not short to the gate conductor. This has been achieved by simply providing ample distance between the diffusion contacting gate such that the contact does not intersect the gate within the process tolerances employed. Borderless contact allows the intersection of a contact to a “border” in the case of a SRAM cell being the gate, by providing means to prevent electrical shorts if the contact intersects the border, thereby permitting the distance between the border and the contact to be reduced. In addition, in a borderless contact it is necessary to contact the borderless element itself such as in the case of a SRAM cell permit contact to the gate conductor. To accomplish this, a separate gate contact mass has previously been used, but this adds another mask step. Additionally, the separate gate contact mass creates further size and overlay tolerance issues. As such, the conventional approaches for forming borderless contacts can fail to provide adequate spacing between the gate and the contact to prevent shorting. These conventional approaches can thereby limit the size of the contacts formed.